? semiconductor components industries, llc, 2009 october, 2009 ? rev. 18 1 publication order number: cs8126/d cs8126 5.0 v, 750 ma low dropout linear regulator with delayed reset the cs8126 is a low dropout, high current 5.0 v linear regulator. it is an improved replacement for the cs8156. improvements include higher accuracy, tighter saturation control, better supply rejection, and enhanced reset circuitry. familiar pnp regulator features such as reverse battery protection, overvoltage shutdown, thermal shutdown, and current limit make the cs8126 suitable for use in automotive and battery operated equipment. additional on ? chip filtering has been included to enhance rejection of high frequency transients on all external leads. an active microprocessor reset function is included on ? chip with externally programmable delay time. during power ? up, or after detection of any error in the regulated output, the reset lead will remain in the low state for the duration of the delay. types of errors include short circuit, low input voltage, overvoltage shutdown, thermal shutdown, or others that cause the output to become unregulated. this function is independent of the input voltage and will function correctly with an output voltage as low as 1.0 v. hysteresis is included in both the reset and delay comparators for enhanced noise immunity. a latching discharge circuit is used to discharge the delay capacitor, even when triggered by a relatively short fault condition. this circuit improves upon the commonly used scr structure by providing full capacitor discharge (0.2 v type). note: the cs8126 is lead compatible with the lm2927 and lm2926. features ? low dropout voltage (0.6 v at 0.5 a) ? 3.0% output accuracy ? active reset ? external reset delay for reset ? protection circuitry ? reverse battery protection ? +60 v, ? 50 v peak transient voltage ? short circuit protection ? internal thermal overload protection ? these are pb ? free devices 1 7 d 2 pak ? 7 dps suffix case 936ab pin 1. v in 2. v out 3. v out(sense) 4. gnd 5. delay 6. reset 7. nc marking diagram *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com a = assembly location w = wafer lot y = year ww = work week g = pb ? free device cs 8126 awlywwg 1 device package shipping ? ordering information cs8126 ? 1ydpsr7g d 2 pak ? 7 (pb ? free) 750/tape & reel cs8126 ? 1ydps7g d 2 pak ? 7 (pb ? free) 50 units / rail ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d.
cs8126 http://onsemi.com 2 delay qs r latching discharge ? + v discharge charge current generator + ? thermal shutdown bandgap reference ? + anti ? saturation and current limit + ? gnd reset pre ? regulator regulated supply for circuit bias v out over voltage shutdown v in error amp delay comparator reset comparator figure 1. block diagram v out(sense)
cs8126 http://onsemi.com 3 maximum ratings* rating value unit power dissipation internally limited ? peak transient voltage (46 v load dump) ? 50, 60 v output current internally limited ? esd susceptibility (human body model) 4.0 kv package thermal resistance: junction ? to ? case, r jc junction ? to ? ambient, r ja 2.1 10 ? 50** c/w c/w junction temperature range ? 40 to +150 c storage temperature range ? 55 to +150 c lead temperature soldering: wave solder (through hole styles only) (note 1) reflow (smd styles only) (note 2) 260 peak 230 peak c c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 1. 10 second maximum. 2. 60 second maximum above 183 c. *the maximum package power dissipation must be observed. **depending on thermal properties of substrate. r ja = r jc + r ca . electrical characteristics (t a = ? 40 c to +125 c, t j = ? 40 c to +150 c, v in = 6.0 to 26 v, i o = 5.0 to 500 ma, r reset = 4.7 k to v cc , unless otherwise noted.) characteristic test conditions min typ max unit output stage (v out ) output voltage ? 4.85 5.00 5.15 v dropout voltage i out1 = 500 ma ? 0.35 0.60 v supply current i out 10 ma i out 100 ma i out 500 ma ? ? ? 2.0 6.0 55 7.0 12 100 ma ma ma line regulation v in = 6.0 to 26 v, i out = 50 ma ? 5.0 50 mv load regulation i out = 50 to 500 ma, v in = 14 v ? 10 50 mv ripple rejection f = 120 hz, v in = 7.0 to 17 v, i out = 250 ma 54 75 ? db current limit ? 0.75 1.20 ? a overvoltage shutdown ? 32 ? 40 v maximum line transient v out 5.5 v ? 95 ? v reverse polarity input voltage dc v out ? 0.6 v, 10 load ? 15 ? 30 ? v reverse polarity input voltage transient 1.0% duty cycle, t < 100 ms, 10 load ? ? 80 ? v thermal shutdown note 3 150 180 210 c 3. guaranteed by design
cs8126 http://onsemi.com 4 electrical characteristics (continued) (t a = ? 40 c to +125 c, t j = ? 40 c to +150 c, v in = 6.0 to 26 v, i o = 5.0 to 500 ma, r reset = 4.7 k to v cc , unless otherwise noted.) characteristic unit max typ min test conditions reset and delay functions delay charge current v delay = 2.0 v 5.0 10 15 a reset threshold v out increasing, v rt(on) v out decreasing, v rt(off) 4.65 4.50 4.90 4.70 v out ? 0.01 v out ? 0.15 v v reset hysteresis v rh = v rt(on) ? v rt(off) 150 200 250 mv delay threshold charge, v dc(hi) discharge, v dc(lo) 3.25 2.85 3.50 3.10 3.75 3.35 v v delay hysteresis ? 200 400 800 mv reset output voltage low 1.0 v < v out < v rtl , 3.0 k to v out ? 0.1 0.4 v reset output leakage current v out > v rt(on) ? 0 10 a delay capacitor discharge voltage discharge latched ?on?, v out > v rt ? 0.2 0.5 v delay time c delay = 0.1 f*. note 4 16 32 48 ms * delay time c delay v delay threshold charge i charge c delay 3.2 4. assumes ideal capacitor package lead description package lead # lead symbol function 1 v in unregulated supply voltage to ic. 2 v out regulated 5.0 v output. 4 gnd ground connection. 5 delay timing capacitor for reset function. 6 reset cmos/ttl compatible output lead. reset goes low after detection of any error in the regulated output or during power up. 3 v out(sense) remote sensing of output voltage. 7 nc no connection.
cs8126 http://onsemi.com 5 typical performance characteristics 0 v in (v) v in (v) i cq ( m a) figure 2. i cq vs. v in over temperature figure 3. i cq vs. v in over r load 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 0 55 50 45 40 35 30 25 20 15 10 5.0 120 110 100 90 80 70 60 50 40 30 20 10 v in (v) v out (v) figure 4. v out vs. v in over temperature 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 v in (v) v out (v) figure 5. v out vs. v in over r load i cq (ma) room temp. r load = 25 r load = 25 room temp. 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 25 c 125 c ? 40 c r load = 6.67 r load = 10 r load = 25 r load = no load 25 c 125 c ? 40 c r load = 10 r load = 6.67 r load = no load output current (ma) 0 100 200 300 400 500 600 700 800 100 80 60 40 20 0 ? 20 ? 40 ? 60 ? 80 ? 100 output current (ma) 0 100 200 300 400 500 600 700 800 6.0 4.0 2.0 0 ? 2.0 ? 4.0 ? 6.0 ? 8.0 ? 10 ? 12 ? 14 figure 6. line regulation vs. output current over temperature figure 7. load regulation vs. output current over temperature li ne r egu l at i on ( m v) load regulation (mv) temp = 25 c temp = 40 c temp = 125 c v in 6.0 ? 26 v temp = ? 40 c temp = 25 c temp = 125 c v in = 14 v
cs8126 http://onsemi.com 6 typical performance characteristics (continued) output current (ma) 0 100 200 300 400 500 600 700 800 figure 8. dropout voltage vs. output current over temperature output current (ma) 0 100 200 300 400 500 600 700 800 100 90 80 70 60 50 40 30 20 10 0 figure 9. quiescent current vs. output current over temperature quiescent current (ma) 900 800 700 600 500 400 300 200 100 0 dropout voltage (mv) 90 80 70 60 50 40 30 20 10 0 rejection (db) freq. (hz) 10 0 figure 10. ripple rejection 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 output current (ma) figure 11. output capacitor esr 10 3 10 2 10 1 10 0 10 ? 4 esr ( ) 10 ? 3 10 ? 2 10 ? 1 10 0 10 1 10 2 10 3 125 c ? 40 c 25 c 25 c 125 c ? 40 c cout = 10 mf, esr = 1 & 0.1 mf, esr = 0 c out = 10 f, esr = 1 & 0.1 f, esr = 0 c out = 10 f, esr = 1.0 c out = 10 f, esr = 10 c out = 47/68 f c out = 47 f c out = 68 f stable region vin = 14 v v dc(lo) v dc(hi) v dh v rl delay (3) reset v rt(off) v rt(on) v rh (1) (2) (2) t delay v dis v out (1) = no delay capacitor (2) = with delay capacitor (3) = max:reset voltage (1.0 v) figure 12. reset circuit waveform reset circuit waveform
cs8126 http://onsemi.com 7 circuit description the cs8126 reset function, has hysteresis on both the reset and delay comparators, a latching delay capacitor discharge circuit, and operates down to 1.0 v. the reset circuit output is an open collector type with on and off parameters as specified. the reset output npn transistor is controlled by the two circuits described (see block diagram). low voltage inhibit circuit this circuit monitors output voltage, and when the output voltage falls below v rt(off) , causes the reset output transistor to be in the on (saturation) state. when the output voltage rises above v rt(on) , this circuit permits the reset output transistor to go into the off state if allowed by the reset delay circuit. reset delay circuit this circuit provides a programmable (by external capacitor) delay on the reset output lead. the delay lead provides source current to the external delay capacitor only when the ?low v oltage inhibit? circuit indicates that output voltage is above v rt(on) . otherwise, the delay lead sinks current to ground (used to discharge the delay capacitor). the discharge current is latched on when the output voltage falls below v rt(off) . the delay capacitor is fully discharged anytime the output voltage falls out of regulation, even for a short period of time. this feature ensures a controlled reset pulse is generated following detection of an error condition. the circuit allows the reset output transistor to go to the off (open) state only when the voltage on the delay lead is higher than v dc(h1) . the delay time for the reset function is calculated from the formula: delay time c delay v delay threshold i charge delay time c delay 3.2 10 5 if c delay = 0.1 f, delay time (ms) = 32 ms 50%: i.e. 16 ms to 48 ms. the tolerance of the capacitor must be taken into account to calculate the total variation in the delay time. figure 13. application diagram gnd v in v out cs8126 c 1 * 100 nf c 2 ** 10 f to 100 f * c 1 is required if the regulator is far from the power source filter. ** c 2 is required for stability. reset delay r rst 4.7 k delay 0.1 f application notes stability considerations the output or compensation capacitor helps determine three main characteristics of a linear regulator: start ? up delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr, can cause instability. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures ( ? 25 c to ? 40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturers data sheet usually provides this information. the value for the output capacitor c 2 shown in the test and applications circuit should work for most applications, however it is not necessarily the optimized solution. to determine an acceptable value for c 2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part.
cs8126 http://onsemi.com 8 step 1: place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. a decade box connected in series with the capacitor will simulate the higher esr of an aluminum capacitor . leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. step 2: with the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. if no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. step 3: increase the esr of the capacitor from zero using the decade box and vary the load current until oscillations appear. record the values of load current and esr that cause the greatest oscillation. this represents the worst case load conditions for the regulator at low temperature. step 4: maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. this point represents the worst case input voltage conditions. step 5: if the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. a smaller capacitor will usually cost less and occupy less board space. if the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. step 6: test the load transient response by switching in various loads at several frequencies to simulate its real working environment. vary the esr to reduce ringing. step 7: raise the temperature to the highest specified operating temperature. v ary the load current as instructed in step 5 to test for any oscillations. once the minimum capacitor value with the maximum esr is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. the esr of the capacitor should be less than 50% of the maximum allowable esr found in step 3 above. calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 14) is: p d(max) v in(max) v out(min) i out(max) v in(max) i q (1) where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current, for the application, and i q is the quiescent current the regulator consumes at i out(max) . once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: r ja 150 c t a p d (2) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja ?s less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. figure 14. single output regulator with key performance parameters labeled smart regulator ? control features i out i in i q v in v out heat sinks a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja . r ja r jc r cs r sa (3) where: r jc = the junction ? to ? case thermal resistance, r cs = the case ? to ? heatsink thermal resistance, and r sa = the heatsink ? to ? ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heat sink manufacturers.
cs8126 http://onsemi.com 9 package dimensions d 2 pak ? 7 (short lead) dps suffix case 936ab ? 01 issue b 0.539 dim min max min max millimeters inches e 0.380 0.420 9.65 10.67 d 0.325 0.368 8.25 9.53 a 0.170 0.180 4.32 4.57 b 0.026 0.036 0.66 0.91 c2 0.045 0.055 1.14 1.40 e 0.050 bsc 1.27 bsc h 0.579 13.69 14.71 l1 a1 0.000 0.010 0.00 0.25 c 0.017 0.026 0.43 0.66 e d l1 c2 c b e e1 d1 h ??? 0.066 ??? 1.68 l 0.058 0.078 1.47 1.98 m l3 0.010 bsc 0.25 bsc 0 8 0 8 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. dimensions d and e do not include mold flash and gate protrusions. mold flash and gate protrusions not to exceed 0.005 maximum per side. these dimensions to be measured at datum h. 4. thermal pad contour optional within dimensions e, l1, d1, and e1. dimensions d1 and e1 establish a minimum mounting surface for the thermal pad. d1 0.270 ??? 6.86 ??? e1 0.245 ??? 6.22 ??? a dimensions: millimeters 0.424 7x 0.584 0.310 0.136 0.040 0.050 pitch soldering footprint* a1 l3 b h l m detail c seating plane gauge plane a 7x m a m 0.13 b e/2 b seating plane a a detail c view a ? a m a m 0.10 b on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. cs8126/d smart regulator is a registered trademark of semiconductor components industries, llc (scillc). publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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